With the rapid development of semiconductor manufacturing technologies, semiconductor device evolves in a direction towards higher component density and higher integration degree.
The improvement in the integration degree of the semiconductor device causes a reduction in the distance between adjacent gate electrode structures, and common-drain MOS transistors are emerged. To accommodate the reduced distance between gate electrode structures in the common-drain MOS transistors, the application of self-aligned scheme in semiconductor processes has become more and more important.
The self-aligned contact (SAC) technology has been applied to fabricate metal contact structures. The SAC technology may realize the etching of relatively deep patterns such as trenches, through-holes, etc., with a relatively high aspect ratio that are disposed between adjacent gate electrode structures, thereby electrically connecting the drain electrodes of the common-drain MOS transistors to the external circuit.
However, issues are commonly found in the current SAC technology as the etching process can be easily terminated and the damages to the through-hole sidewalls are relatively large.
The disclosed etching method and fabrication method of semiconductor structures are directed to at least partially solving one or more problems set forth above and other problems.